1. Field of the Invention
Embodiments of the invention relate to a semiconductor device.
2. Description of the Related Art
For a high voltage integrated circuit (HVIC), an element separation scheme using a high voltage junction has been known traditionally in which a high potential side (a high side) region and a low potential side (a low side) region provided on a single semiconductor chip are electrically separated from each other by a high voltage junction termination region (HVJT) that is provided between the regions.
It is known that a high voltage n-channel metal oxide semiconductor field effect transistor (MOSFET) functioning as a level-raising circuit is arranged in the HVJT (see, for example, Japanese Laid-Open Patent Publication Nos. H9-283716 and 2005-123512). Signal transmission is executed between the high potential region and the low potential region through these level-shift circuits.
Configuration of traditional HVICs will be described. FIGS. 23, 24, 25, and 26 are plan diagrams examples of a planar layout of essential portions of traditional semiconductor devices. FIGS. 23 and 24 are respectively FIGS. 1 and 8 of Japanese Laid-Open Patent Publication No. H9-283716 and FIG. 26 is FIG. 6 of Japanese Laid-Open Patent Publication No. 2005-123512. The traditional semiconductor device depicted in FIG. 23 includes a high potential side region 211 and a low potential side region 212 on a single p−-type semiconductor substrate 201, and is configured to electrically separate these regions from each other using an HVJT 213. The high potential side region 211 is an n-type region 202 provided on the p−-type semiconductor substrate 201. The low potential side region 212 is a portion of the p−-type semiconductor substrate 201 located farther outward (closer to the periphery of the chip) than an n−-type region 203.
The HVJT 213 is the n−-type region 203 that surrounds the periphery of the n-type region 202. A portion 204 of the p−-type semiconductor substrate 201 (hereinafter, referred to as “p−-type separation region”) is in between the n-type region 202 and the n−-type region 203 to have a substantially U-shaped planar layout starting from the low potential side region 212 and returning to the low potential side region 212 through the HVJT 213 and the high potential side region 211. The p−-type separation region 204 electrically separates from other portions, portions 202a and 203a of a portion in which the n-type region 202 and the n−-type region 203 are continuous with each other. An n-channel MOSFET used as a level shifter 214 is arranged in the portions 202a and 203a surrounded by the p−-type separation region 204. A reference numeral “217” denotes a parasitic diode in a region other than the level shifter 214 of the HVJT 213 (similarly in FIGS. 24 to 26).
In the traditional semiconductor device depicted in FIG. 24, a p−-type separation region 205 arranged in a substantially rectangular frame planar layout inside the n-type region 202 separates a portion 202b on the outer side of the n-type region 202 (hereinafter, referred to as “peripheral edge portion”) and a portion on the inner side of the n-type region 202 (hereinafter, referred to as “central portion”) from each other. An n-channel MOSFET is arranged to be used as the level shifter 214 that uses a portion of the n−-type region 203 as a drift region. The arrangement of the high potential side region 211, the low potential side region 212, and the HVJT 213 of the traditional semiconductor device depicted in FIG. 24 is same as that of the traditional semiconductor device depicted in FIG. 23 (similarly in FIGS. 25 and 26).
In the traditional semiconductor device depicted in FIG. 25, a p-type separation region 206 arranged in a substantially C-shaped planar layout inside the n-type region 202 separates a portion 202c along three sides of the peripheral edge portion of the n-type region 202 arranged in a rectangular planar layout and the central portion of the n-type region 202 from each other. An n-channel MOSFET is arranged to be used as the level shifter 214 that uses, as a drift region, a portion of the n−-type region 203 facing the high potential side region 211 sandwiching the n−-type separation region 206 therebetween.
A portion 202d of the n-type region 202 along the other one side not separated by the p−-type separation region 206 has a potential that is fixed at the maximal potential of the high potential side region 211. Resistance of a diffusion region is used as level-shift resistance, between the portion 202d whose potential is fixed at the maximal potential of the high potential side region 211 and the drain region not depicted of the re-channel MOSFET that constitutes the level shifter 214. A reference numeral “208” denotes a p−-type region constituting a parasitic diode 217.
In the traditional semiconductor device depicted in FIG. 26, a portion of the HVJT 213 is separated by trenches 207 (for example, at two points) and, in the regions each surrounded by the trench 207, an n-channel MOSFET and a p-channel MOSFET are arranged that are used as the level shifters 214 (214a and 214b). Reference numerals “215” and “216” each denote a wire.
With a configuration to use a portion of the HVJT 213 as the level shifter 214 as above, the p−-type separation regions 204 to 206 or the trenches 207 electrically separate the region having the inner circuits arranged therein of the high potential side region 211 and the level shifter 214 of the HVJT 213 from each other. High potential wiring that extends from the low potential side region 212 to the high potential side region 211 passing over the HVJT 213 is thereby unnecessary and the reliability is therefore high. Compared to a configuration to have the level shifter 214 arranged in a region other than the HVJT 213, the chip size may be reduced (shrunk) by the footprint of the level shifter 214.
To stably secure a high breakdown voltage, a high voltage diode, a high voltage MOSFET, and the like each often include a field plate (FP) arranged to extend on an interlayer insulating film as an edge termination structure. A resistive field plate (RFP) and the like that, inside the interlayer insulating film, includes a thin film resistive layer arranged in a spiral planar layout to surround the periphery of the high potential side region starting from the high potential side region reaching the low potential side region are known as field plates (see Japanese Laid-Open Patent Publication Nos. 2000-022175 and 2003-008009, International Patent Publication No. 2003-533886, and Japanese Patent Publication No. 5748353).